This invention relates generally to integrated latch or flip-flop circuits, and, more particularly, to a technique for correcting errors in the output signal of the latch due to single event upsets or on-chip coupling noise.
A single event upset (SEU) is the result of an ion transitioning through a semiconductor structure and, in doing so, causing charge to be deposited on critical circuit nodes within that structure. In a CMOS logic circuit, such as a latch circuit, this can cause an unintended switch in the output logic state, creating potentially catastrophic consequences for the system. In the case of storage cells and latch circuits, the primary SEU problem lies in the feedback path, where amplification and feedback of noise on a critical node can permanently change the cell""s logic state.
Known SEU hardening or error-correcting techniques for CMOS logic include the use of redundant circuit paths, and for memory cells it is known to use cross-coupled resistors or capacitors. Multiple circuit paths provide redundancy and allow implementation of voting schemes to reduce the effect of SEUs. The addition of cross-coupled resistors and capacitors in a storage cell slows the cell""s ability to latch false data. However, each of these techniques has its drawbacks. The typical voting scheme uses appended digital logic to recombine the redundant paths, which complicates clocking of sequential circuitry and may actually exacerbate the effects of the SEU. The addition of cross-coupled resistors and capacitors in a storage cell involves more complicated fabrication processes and results in slower response to all input signals, thereby decreasing its operating speed.
A need remains, therefore, for a robust latch circuit solution that substantially reduces errors due to SEUs or on-chip noise coupling.
According to the present invention an error-correcting latch has the error-correcting circuitry built directly into the feedback path of the latch to ensure that errors due to SEUs or on-chip noise coupling are substantially reduced and are not fed through to the output as in prior art designs. The error-correcting latches of the present invention use a two-out-of-three voting scheme that is embedded into the feedback path of the latch itself.
A first embodiment of an error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate.
A second embodiment of an error-correcting partial latch stage includes a gated inverter having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a pass gate having an input coupled to the output of the gated inverter, an output, and a control node for receiving the control signal, an inverter having an output coupled to the output of the pass gate, and a correcting inverter stage having a first input coupled to the output of the gated inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the input of the inverter for providing a data output signal.
A third embodiment of an error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output, a first delay path having an input coupled to the output of the inverter and an output, a second delay path having an input coupled to the output of the inverter and an output, and a correcting inverter stage having a first input coupled to the output of the inverter, a second input coupled to the output of the first delay path, a third input coupled to the output of the second delay path, and an output coupled to the output of the second pass gate.
A fourth embodiment of an error-correcting latch stage includes a gated inverter having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a pass gate having an input coupled to the output of the gated inverter, an output, and a control node for receiving the control signal, an inverter having an output coupled to the output of the pass gate, a first delay path having an input coupled to the output of the gated inverter and an output, a second delay path having an input coupled to the output of the gated inverter and an output; and a correcting inverter stage having a first input coupled to the output of the gated inverter, a second input coupled to the output of the first delay path, a third input coupled to the output of the second delay path, and an output coupled to the input of the inverter for providing a data output signal.
A first embodiment of the correcting inverter stage includes first, second, and third two-input AND gates coupled to a three-input NOR gate. A second embodiment of the correcting inverter stage includes first, second, and third two-input NAND gates coupled to a three-input NAND gate. A third embodiment of the correcting inverter stage includes a CMOS transistor circuit comprising three differential PMOS stages coupled to three cascoded NMOS stages. Each of the correcting inverter stage embodiments preferably operates according to the same logic function.
For the first and second embodiments, a full latch stage includes three interconnected partial latch stages with an optional output correcting inverter stage for providing an extra measure of immunity to SEU events. A full latch stage for the first and second embodiments includes first, second, and third partial latch stages, each latch stage having an input for receiving a data input signal, a correcting inverter stage, and an output for providing an output signal. The output signals of the first, second, and third partial latch stages can be logically combined to provide the final output signal, or simply one of the individual outputs can be used as the final output signal.
If desired, an error-correcting full D-type master-slave flip-flop can be built having a master latch stage including first, second, and third partial latch stages, each latch stage having an input for receiving a data input signal, a correcting inverter stage, and an output for providing an intermediate signal, and a slave latch stage coupled to the master last stage including first, second, and third partial latch stages, each latch stage having an input for receiving the intermediate signal, a correcting inverter stage, and an output for providing an output signal. An error-correcting full D-type master-slave flip-flop can also be built using the delayed correcting latch, or a combination of the two.